The Xilinx LogiCORE™ IP AXI Central Direct Memory Access (CDMA) core is a soft Xilinx Intellectual Property (IP) core for use with the Vivado® Design Suite. The AXI CDMA provides high-bandwidth Direct ...

The proposed MURO-TRNG architecture is designed using VHDL, implemented on the Artix 7, Kintex-7, and Zynq7000 FPGAs, and simulated by the Xilinx Vivado 2015.2 tool. The designed and implemented ...

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

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Hardware implementations for basic digital circuit designs in Verilog with a Xilinx Artix-7 FPGA chip on a Digilent Basys 3 development board.