PCIe technology is set to be leveraged as an important component in the AI infrastructure marketplace. According to the “PCI ...

This collaboration highlights GUC's commitment to deliver comprehensive and innovative design solutions, enabling customers ...

A jury in Wilmington, Delaware, has found that Qualcomm’s latest AI-PC processors – based on the ARM instruction set – are ...

This funding will support the continued development and demonstration of Strategic Radiation Hardened (SRH) high reliability ...

The partnership between Silvaco and Micon Global is expected to drive Silvaco’s expansion across the EMEA market, leveraging Micon Global’s expertise to enhance client access to Silvaco’s design ...

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. The PHY’s flexible ...

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. The PHY’s flexible ...

Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Controller is compliant with the PCI Express ... Rambus ...

The eSi-SPI core is a Serial Peripheral Interface that can be used to implement full-duplex, synchronous, serial communications between ICs. The eSi-SPI core can operate as a SPI master or slave.

The 10/100/1G Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of designs with a 10/100/1000M Ethernet ...

The SmartDV Verification IP (VIP) for SSI (Synchronous Serial Interface) is a full-duplex synchronous serial interface and can connect to a variety of external analog-to-digital (A/D) converters, ...

The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication factors up to 8192, allowing the PLL to run off of ...